Electrically erasable programmable read only memories (EEPROMs) are well known in the art. EEPROMs, like other memory devices, include a plurality of memory cells, each capable of storing a single binary digit (bit). The binary value stored in each cell is programmed to a logical zero or logical one value by placing an appropriate charge on the floating gate of a MOS transistor forming the cell. By altering the charge stored on the floating gate, the threshold voltage required to be applied to the control gate of the floating gate transistor is changed to either a voltage level representing a logical one or a voltage level representing a logical zero. When the memory cell is accessed for reading, a voltage is applied to the control gate which is greater than the threshold voltage associated with a logical one but less than the threshold voltage associated with a logical zero. In this manner, with a read signal applied to the control gate, the floating gate transistor turns on if it stores a logical one, but remains off if it stores a logical zero. A sense amplifier, well known in the art, is used to determine if the transistor is on or off.
FIG. 1 is a schematic diagram of a typical prior art EEPROM. The circuit of FIG. 1 allows for flash erasure of all bits stored in the memory array, that is to say the cells are written on a bit-by-bit, or word-by-word basis, the array is read on a word-by-word basis, and the array is erased by erasing all cells simultaneously to the logical one state. As shown in FIG. 1, flash erase EEPROM circuit 100 includes a plurality of row lines 101-1 through 101 N, and a plurality of columns or "bit lines" 102-1 through 102-M. Associated with each combination of row line and bit line is one of floating gate memory cell transistors 105-1-1 through 105-N-M. The control gates of each memory cell transistor 105-1-1 through 105-N-M are connected to their associated row lines 101-1 through 101-N. The drains of each memory cell transistor are connected to their associated bit lines. The sources of each memory cell transistor are connected in common to the drain of erase transistor 112, as is more fully described later.
Power is supplied to each bit line 102-1 through 102-M through column select transistors 104-1 through 104-M, each receiving an appropriate column select signal on their gate leads 103-1 through 103-M, respectively. The entire block of array transistors 105-1-1 through 105-N-M is selected by block transistor 106 receiving a block select signal (for example, a decoded signal based on one or more most significant address bits, with the least significant address bits defining individual memory cells within the block) applied to its gate lead 107. When block select transistor 106 is turned on, the block containing memory cells 105-1-1 through 105-N-M is selected and when one or more column select transistors 104-1 through 104-M are turned on, desired ones of bit lines 102-1 through 102-M are selected. This enables the appropriate voltages to be applied to desired ones of bit lines of 102-1 through 102-M.
For example, a programming voltage VPP (typically 12 volts during programming and 17 volts during erasure) is selectively applied to selected bit lines when programming/erase control circuitry 119 provides a signal to the gate of programming/erase transistor 108 causing transistor 108 to conduct. Similarly, during the read operation, the voltage level of a selected bit line is applied via transistor 110 to sense amplifier 111 in order to determine the value of the bit stored in a selected memory cell.
The operation of circuit 100 in the programming, reading, and erasure modes is depicted in Table 1. During programming, memory array transistors are written individually by selectively addressing desired rows and columns. Thus, a selected row receives a voltage (typically approximately 14 volts) thereby enabling the memory transistors within the row to turn on. At the same time, deselected rows each receive a logical zero, preventing the memory transistors of the deselected rows from turning on. For those memory cells within the selected row which are to store a logical one (floating gate uncharged, relatively low control gate threshold voltage), their associated bit lines receive a logical zero by causing their associated column select transistors 104-1 through 104-M to remain off. In other words, columns whose memory cells are to store a logical one are deselected. Conversely, columns associated with memory cells which are to store a logical zero are selected by turning on their associated column select transistors 104-1 through 104-M, and programming/erase control circuitry 119 causes transistor 108 to turn on, thereby applying programming voltage VPP to the selected columns. This action causes the memory transistors which are to store a logical one to turn on and, with a relatively high voltage VPP applied to their drains, 0 volts on their sources, and a high voltage (typically 14 volts) applied to the control gate, cause hot electrons to be injected from the drain to the floating gate, thereby increasing the control gate threshold voltage to that threshold voltage associated with a logical zero.
During reading of circuit 100, individual memory cells are selected by an appropriate combination of column select and row select signals, allowing the data stored in the selected memory cell to be detected by sense amplifier 111. Thus, for example, to read the data stored in memory cell 105-1-1, row line 101-1 is selected by applying voltage VCC of approximately 5 volts with row lines 101-2 through 101-N being deselected by applying zero volts. Bit line 102-1 is selected by causing column select transistor 104-1 to turn on, while deselecting bit lines 102-2 through 102-M by causing column select transistors 104-2 through 104-M to be turned off. During the read operation, programming/erase transistor 108 is turned off, and a reference voltage VREF (typically 2.5 volts) is applied to the gate of pass transistor 110. This causes the voltage on the selected bit line 102-1 to be applied to the input lead of sense amplifier 111, which in turn provides an output signal indicating whether the selected memory cell 105-1-1 stores a logical zero or a logical one.
When memory cell 105-1-1 stores a logical one, its control gate threshold voltage is less than the read voltage applied to row line 101-1, and thus memory cell transistor 105-1-1 is turned on pulling the input lead of sense amplifier 111 low through transistors 110, 106, 104-1, 105-1-1, and 112. Conversely, when memory cell 105-1-1 stores a logical zero, its control gate threshold voltage is greater than the read voltage applied to row line 101-1, memory cell transistor 105-1-1 does not turn on, and the input lead of sense amplifier 111 is not pulled low. Thus, sense amplifier 111 can detect the two possible values of the bits stored by the memory selected for reading.
During erasure, memory cells 105-1-1 through 105-N-M are "flash" erased, i.e., all erased simultaneously such that they store logical zeros. This is accomplished by applying 0 volts to the row lines connected to the control gates of the memory transistors, a high voltage (typically 17 volts) to the bit lines connected to the drains of the memory cell transistors, and leaving the erase line, which is connected to the sources of the memory cell transistors, floating.
Of importance, during programming and erasing of memory cells 105-1-1 through 105-N-M, a relatively high voltage VPP is applied to selected bit lines 102-1 through 102-M. This requires all transistors between VPP terminal 120 and bit lines 102-1 through 102-M, as well as transistor 110 located between VPP terminal 120 and the input lead of sense amplifier 111, to be fabricated to ensure they will not break down due to the use of the relatively high voltage VPP. MOS transistors utilized in this fashion, when subjected to relatively high voltages, are subject to gated diode breakdown which, of course, must be eliminated if the device is to operate properly and be reliable over a long period of time. A gated diode is a PN junction located under the gate electrode. When the gate electrode is grounded, the breakdown voltage of the gated diode is much lower than the breakdown voltage of the gated diode when the gate is not grounded. Furthermore, the gated diode breakdown voltage is lower with thinner gate oxides and shallower junctions depths. In order to prevent such gated diode breakdown problems, these transistors are typically formed utilizing a relatively thick gate oxide (typically 350 .ANG. thick) as compared with the relatively thin gate oxide utilized by the peripheral transistors in the speed path, such as the transistors (not shown) of sense amplifier 111, and the transistors of the address buffers, also not shown, which typically have gate oxide thicknesses on the order of 250 .ANG.. While the use of thick gate oxide satisfies the requirement that these transistors be impervious to breakdown problems when a high programming/erasure voltage VPP is applied, it has a deleterious effect of decreasing the gain of these transistors, which in turn decreases their switching speed. A decreased switching speed of any transistors located between sense amplifier 111 and the memory array transistors 105-1-1 through 105-N-M decreases the speed of operation of the device, clearly an undesirable feature.
FIG. 2 is a top view of a pair of typical prior art EEPROM memory cells including N+ drain diffusion 201, which is connected via electrical contact 202 to metallization layer 203. Cell 200 also includes a first layer of polycrystalline silicon 204 which serves as the floating gate of the EEPROM memory transistor, and a second layer of polycrystalline silicon 205 which serves as the control gate and which forms part of a row line. As described above with regard to the schematic diagram of FIG. 1, programming, reading, and erasure of cell 200 is all performed from the drain 201 side of the memory cell.